Low Overhead Dynamic Binary Translation on ARM
The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction set, while retaining binary compatibility with previous versions of the ARM architecture through AArch32, a 32-bit execution mode. Most hardware implementations of ARMv8 processors support both AArch32 and AArch64, which comes at a cost in hardware complexity.
We present MAMBO-X64, a dynamic binary translator which executes 32-bit ARM binaries using only the AArch64 instruction set. We have evaluated the performance of MAMBO-X64 on three existing ARMv8 processors which support both AArch32 and AArch64 instruction sets. The performance was measured with SPEC CPU2006 and PARSEC by comparing the runtime of 32-bit benchmarks running under MAMBO-X64 with the same benchmark running natively. On both sequential and multi-threaded benchmarks, we achieve a geometric mean overhead of less than 7.5% on Cortex-A53 processors and a performance improvement of 1% on X-Gene processors.
MAMBO-X64 achieves such low overhead by novel optimizations to map AArch32 floating-point registers to AArch64 registers dynamically, generate traces that harness hardware return address prediction, and efficiently handle operating system signals.
Mon 19 Jun
|16:10 - 16:35|
|16:35 - 17:00|
Buddhika ChamithIndiana University, Luke DalessandroIndiana University, Bo Joel SvenssonChalmers University of Technology, Sweden, Ryan R. NewtonIndiana UniversityMedia Attached
|17:00 - 17:25|
Amanieu d'AntrasUniversity of Manchester, Cosmin GorgovanUniversity of Manchester, Jim GarsideUniversity of Manchester, Mikel LujanMedia Attached
|17:25 - 17:50|
Qirun ZhangUniversity of California, Davis, Chengnian SunUniversity of California, Davis, Zhendong SuUniversity of California, DavisMedia Attached